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This paper presents a novel jitter reduction technique for a voltage-controlled ring oscillator (VCRO). This technique is helpful in employing VCRO-based circuits like Analog to Digital Converter (ADC), Phase Locked Loop (PLL) and time-based circuits whose performance is severely degraded by high jitter. In the proposed technique, the jitter is extracted using Excess Phase Discrimination (EPD) block and is transformed into Pulse Width Modulated (PWM) signal, which is then fed into the Phase Compensator (PC) block. This block reduces the jitter by about half its value after enabling the Single Ended Injection Locking (SEIL). The proposed work is designed in SCL 180 nm CMOS technology at 1.8 V supply. On enabling the proposed circuit, the Root Mean Square (RMS) jitter reduces from 5.94 to 2.58 ps (about 56%) for VCRO running at 58 MHz and consumes a total power of 375.84 μ W. The overall performance of the proposed circuit does not vary much in the post-layout simulations, hence demonstrating the effectiveness of the proposed technique. [ABSTRACT FROM AUTHOR]

This study proposes a control method for transferring power generated by a solar photovoltaic system. The control algorithm, called MVF-DSOGI-PLL or Multi-Variable Filter Dual Second-Order Generalized Integrator Phase-Locked Loop), accurately estimates symmetrical components, phase angle, and positive sequence voltages of the Common Point of Interface (CPI) in distorted grid conditions. The approach creates a compensatory current to reduce PQ difficulties by extracting the size of the basic current load undergoing operation employing the SOGI method. These systems can operate in either modes of PV-DSTATCOM or DSTATCOM, depending on solar insolation's availability. The simulation models of the grid-interfaced SPV systems are developed in Matlab/Simulink to evaluate the performances of the suggested control method. The results of simulation demonstrate that the suggested control systems efficiently transfers the power generated by PV arrays to a grid while performing tasks like load balancing, power factor correction (PFC), and harmonics reduction. Furthermore, the MVF-DSOGI-PLL-based control algorithm successfully mitigates PQ issues in distribution networks with weak grids, ensuring that PQ levels remain between a limited set by the IEEE-519 standard. A laboratory prototype of the proposed system is implemented to assess its steady states and dynamic efficient under fluctuating solar insolation, and load imbalance distortions. [ABSTRACT FROM AUTHOR]

This paper proposes a novel stabilizing control method aimed at overcoming the instability challenges posed by the negative incremental resistance characteristics of a constant power load (CPL) within an autonomous microgrid (MG). The proposed stabilization technique integrates a power derivative-integral term with conventional droop control, strategically applied to enhance the MG's dynamic stability in the presence of CPL. The considered MG model, encompassing three inverter-based distributed generations (DGs), a constant impedance load (CIL), and CPL, is meticulously developed and simulated using MATLAB environment. Phase Locked Loop (PLL) is employed to synchronize the CPL with MG. The proposed controller is a key highlight, featuring optimally designed and tuned controller parameters for all DGs, CPL, and PLL. Particle Swarm Optimization (PSO) and Genetic Algorithm (GA) are employed to address the challenges linked to the laborious tuning process of controllers. The simulation results, which include scenarios involving three-phase faults and step changes, provide compelling evidence of the proposed controller's superior performance compared to conventional droop scheme. Furthermore, a comparative analysis is conducted to affirm and quantify the enhancements achieved through the proposed modified droop PSO-based MG controller concerning transient response. The results obtained emphasize the effectiveness of the proposed approach in simultaneously minimizing both overshoot and settling time. In comparison with the conventional controller, the proposed controller demonstrates a substantial decrease in percentage overshoot for the active power of DG3 and DC voltage of the CPL, with values of 93.89 and 99.9%, respectively. The corresponding improvements in settling time are notable, showcasing reductions of 83.11% for the active power of DG3 and 66.1% for the DC voltage of the CPL. When compared to the GA-based controller, the proposed controller exhibits significant percentage overshoot reductions for and DC voltage of the CPL, achieving 79.42 and 99.8%, respectively. Additionally, the settling time records noteworthy improvements, with reductions of 76.19% for the active power of DG3 and 57.57% for the DC voltage of the CPL. To further validate the real-world applicability and effectiveness of the proposed method, a real-time digital simulator (RTDS) is employed. The RTDS experiments results confirm the proposed scheme's ability to enhance MG stability, substantiating the simulation findings. This holistic approach, encompassing theoretical modeling, simulation studies, and real-time validation, establishes the proposed stabilizing control method as a promising and effective solution for mitigating instability issues associated with CPL in autonomous MGs. [ABSTRACT FROM AUTHOR]

Numerous studies have introduced a variety of synchronization techniques that involve many structures. However, since the majority of synchronization methods influence or increase the system states from a stability perspective, these methods necessitate retuning the controller parameters, reconstructing a converter controller, or employing a different control construction. This paper proposes a novel, yet simple and straightforward, method for implementing a synchronization technique concept based on the conventional synchronization method known as the "dark lamp" process. Since the proposed method is based on logic functions, there is no additional state in the entire system of the model, which is the cornerstone of this paper. The proposed method is validated and studied in a time–domain simulation environment, specifically a PSCAD/EMTDC. The proposed new synchronization technique in this paper overcomes the discussed synchronization techniques in the literature by dispensing with the need either to use a phase-locked loop (PLL) or to retune the controller parameters and, furthermore, does not increase the system state equation. Meanwhile the proposed techniques in the literature increase the system state equation by at least two states, which affects the entire system performance and stability. The results of this paper show promising and important outcomes that will further the study of the synchronization technique. [ABSTRACT FROM AUTHOR]

Liquid level detection system is an essential core functional component of automatic clinical medical testing instrument. The conventional liquid level detection method has low detection accuracy and sensitivity, and may have the problem of false detection, which may lead to the inaccurate test results. This paper presents a high sensitivity liquid level detection system based on the principle of variable capacitance. When the sampling probe contacts the liquid level, the probe capacitance will change. The liquid level detection circuit board judges whether the probe contacts the liquid level by sensing the change of probe capacitance. When judging the liquid level signal, the combination of slope detection and amplitude detection is used. The liquid level detection circuit board takes the phase-locked loop(PLL) circuit as the center to detect the change of the capacitance. The reference signal of the PLL is set as a square wave of 375kHz. The double tube probe is used as a part of the tuning capacitor of the voltage controlled oscillator to control the frequency of the output signal, which can realize the rapid phase locking. The experimental results show that the system has accurate detection results, high sensitivity, stable and reliable operation, good dynamic response performance in the case of large and small liquid volume. Compared with other liquid level detection methods based on machine vision, ultrasonic, optics and so on, the proposed liquid level detection system has simpler structure and lower cost, it can avoid the problems of collision, carryover contamination and empty suction by controlling the depth of sampling needle inserted into liquid. [ABSTRACT FROM AUTHOR]

This study proposes a novel double closed-loop robust control strategy based on a power switching affine model of three-phase voltage source converters (VSCs). The aim is to overcome the challenges posed by inaccurate mathematical models, complex controller configurations, indirect switching control, and performance degradation under circuit parameters uncertainty or load variation in conventional methods. These conventional methods rely on linearization models, duty ratio regulation, and pulse width modulation (PWM) technologies. The contributions of work are the following: (1) A two-dimensional (2D) power switching affine model is constructed without any approximation or averaging. (2) The proposed approach achieves direct switching control of three-phase VSCs, eliminating the need for complex rotation coordinate transformation, PWM, and phase locking loop (PLL), which are utilized in traditional control methods. (3) The rigor of the system stability analysis is enhanced based on the 2D power switching model compared to the existing three-dimensional (3D) current switching model. (4) A simple control structure with only two control parameters is employed to address circuit parameter uncertainties. The effectiveness and superiority of the proposed method is validated through simulation and experimental comparison results. [ABSTRACT FROM AUTHOR]

This work deals with doubly fed induction generator (DFIG) modeling and stability when connected to weak AC grids. A detailed state-space model that includes the phase-locked loop (PLL) is developed. This work aims to determine the influence of the network's strength on DFIG stability through the short-circuit ratio (SCR). The critical values of the proportional control parameters of the grid-side and rotor-side converters (RSC and GSC), as well as PLL, which make the system unstable, are calculated for different SCR values. Finally, PSCAD/EMTDC dynamic simulations are used to validate the critical control parameters obtained by studying the eigenvalues of the DFIG state-space model regarding system stability. [ABSTRACT FROM AUTHOR]

The operational performance of grid‐connected active front‐end converters (AFEs) faces challenges arising from the intricate interplay among phase‐locked loop (PLL) non‐linearities, grid impedance, and conventional control strategies, resulting in compromised stability. This study introduces a refined approach to dynamic model predictive control (MPC) by integrating recursive least squares (RLS) for the precise estimation of physical model parameters, thereby addressing stability concerns. Unlike conventional methodologies, the proposed enhanced RLS‐based MPC approach, equipped with an auto‐tuning feature, allows for the design of controllers without a prerequisite understanding of exact external dynamics. Notably, this technique exhibits exceptional disturbance rejection capabilities. The evaluation of the cost function at each sampling interval facilitates the determination of optimal switching states based on predicted variables. Gate pulses for the switches of the AFEs are generated accordingly. Employing a simulation platform, the proposed control structure's performance across varied conditions is comprehensively assessed, encompassing alterations in grid impedance and system non‐linearities. The method adeptly integrates inherent non‐linearities within the system, showcasing exceptional robustness in diverse dynamic scenarios. To further substantiate the efficacy of the proposed control system over conventional approaches, simulation results are validated using a laboratory hardware platform equipped with Typhoon HIL and dSPACE real‐time emulators, providing tangible evidence of the proposed control system's effectiveness in real‐world hardware setups. The multifaceted approach, encompassing precise parameter estimation, predictive control, auto‐tuning, disturbance rejection, robust design, and real‐time evaluation, collectively establishes a resilient foundation for enhancing and maintaining the overall stability of the system across diverse operating scenarios. [ABSTRACT FROM AUTHOR]

In this article, a dual third-order generalized integrator-based phase-locked loop (DTOGI-PLL) and an additional degree of freedom-based frequency locked loop (ADF-FLL) control approaches are utilized on a voltage source converter (VSC) to control an isolated microgrid system under different operating conditions. The proposed adaptive approaches provide a fast dynamic response with a precise estimation of frequency, phase angle, and fundamental load current component compared to that of the TOGI-PLL and least mean square (LMS) algorithms. An ADF-FLL allows closed-loop poles to perform more optimally, resulting in faster dynamic performance without compromising filtering capability. Moreover, the proposed adaptive approaches with VSC provide power support, load leveling, harmonic eliminations, and enhance the isolated microgrid's overall power quality during dynamics in load and energy sources. A solar PV (SPV) array with perturb & observe (P&O) MPPT control is interfaced at the DC link of a bidirectional controller (BDC) to draw maximum solar power. Through dc-link voltage control, the BDC with energy storage system (ESS) ensures the appropriate power flow and power equilibrium between energy sources and load. The Simulation and test results show the dynamic performance of the isolated microgrid is examined under different operational scenarios. [ABSTRACT FROM AUTHOR]

Electrothermal piezoresistive resonant cantilever sensors have been fabricated with embedded actuating (heating resistor) and sensing (piezo resistors) parts, with the latter configured in a Wheatstone bridge circuit. Due to the close spacing between these two elements, a direct thermal parasitic effect on the resonant sensor during the actuating-sensing process leads to asymmetric amplitude and reversing phase spectral responses. Such a condition affects the precise determination of the cantilever's resonant frequency, f0. Moreover, in the context of phase-locked loop-based (PLL) resonance tracking, a reversing phase spectral response hinders the resonance locking due to its ambiguity. In this work, a replica of the baseline spectral was applied to remove the thermal parasitic effect on the resonance spectra of the cantilever sensor, and its capability was simulated through mathematical analysis. This replica spectral was subtracted from the parasitized spectral using a particular calculation, resulting in optimized spectral responses. An assessment using cigarette smoke particles performed a desired spectral shifting into symmetrical amplitude shapes and monotonic phase transitions, subsequently allowing for real-time PLL-based frequency tracking. [ABSTRACT FROM AUTHOR]

For weak grid scenario with high new energy proportion, large fluctuations of load are prone to cause low-voltage ride through. Moreover, stator transient magnetic flux will cause overvoltage and overcurrent problems in the rotor of doubly fed induction generator. Based on model predictive control, a control strategy for transient flux linkage and reactive power compensation is proposed. Firstly, regarding the issue of reactive power allocation of grid side converters (GSC) and rotor side converters (RSC), an allocation strategy is derived under minimizing winding energy loss on case of low-voltage ride through, enabling the wind energy conversion system to provide reactive power support during grid voltage recovery process. Meanwhile, an improved mixed second- and third-order generalized integrator (MSTOGI) phase-locked loop (PLL) is used to extract the positive and negative sequence components of the power grid voltage, further for RSC control. Secondly, in response to power grid faults, considering the influence of stator DC transient flux and negative sequence flux components on rotor current, by injecting rotor transient compensation current and stator flux feedforward compensation into RSC, the rotor impulse voltage and loop current are reduced. Moreover, combined with model predictive control algorithm, a control strategy of rotor current is designed. Finally, a simulation platform is built to validate the effectiveness of the proposed method based on comparing with several traditional vector control low-voltage ride through methods. [ABSTRACT FROM AUTHOR]

This paper proposes an improved event‐driven (ED) model to improve the simulation efficiency of a mixed‐signal charge‐pump phase locked loop (CP‐PLL) design for a frequency‐modulated continuous‐wave (FMCW) chirp generation. The improvement mainly comes into three parts. First, we update the data only when it changes during the previous trigger. Second, we save the data at the triggering moment of the reference clock to achieve uniform sampling for better noise characterization. Furthermore, we propose a simplified model that is specifically optimized for the third‐order loop filter (LF). This article presents a detailed design flow of the improved ED model, and we apply it to the simulation of the FMCW chirp generation. Compared to the conventional transistor‐level simulation, our proposed model reduces the simulation time to less than 1 s, which leads to a reduction of the simulation time by five or six orders of magnitude. [ABSTRACT FROM AUTHOR]

A fully integrated 24-GHz radar transceiver with one transmitter (TX) and two receivers (RXs) for compact frequency modulated continuous wave (FMCW) radar applications is here presented. The FMCW synthesizer was realized using a fractional-N phase-locked loop (PLL) and programmable chirp generator, which are completely integrated in the proposed transceiver. The measured output phase noise of the synthesizer is −80 dBc/Hz at 100 kHz offset. The TX consists of a three-bit bridged t-type attenuator for gain control, a two-stage drive amplifier (DA) and a one-stage power amplifier (PA). The TX chain provides an output power of 13 dBm while achieving <0.5 dB output power variation within the range of 24 to 24.25 GHz. The RX with a direct conversion I-Q structure is composed of a two-stage low noise amplifier (LNA), I-Q generator, mixer, transimpedance amplifier (TIA), a two-stage biquad band pass filter (BPF), and a differential-to-single (DTS) amplifier. The TIA and the BPF employ a DC offset cancellation (DCOC) circuit to suppress the strong reflection signal and TX-RX leakage. The RX chain exhibits an overall gain of 100 dB. The proposed radar transceiver is fabricated using a 65 nm CMOS technology. The transceiver consumes 220 mW from a 1 V supply voltage and has 4.84 mm2 die size including all pads. The prototype FMCW radar is realized with the proposed transceiver and Yagi antenna to verify the radar functionality, such as the distance and angle of targets. [ABSTRACT FROM AUTHOR]

Summary: This paper proposes a fractional delay (FD) Newton structure for Lagrangian interpolation in single phase grid integrated photovoltaic (PV) system. The structure has been designed for achieving shunt compensation and as a phase locked loop circuit for synchronization. The designed controller performs multiple tasks of feeding the active power to meet the load demand and simultaneously providing reactive power compensation, power factor improvement, and compensating other power quality voltage and load current harmonics. Further, synchronization poses a severe challenge in integrating the PV power electronic converters to the grid. The FD filter is used to discretize the continuous time signal at any time instant using interpolation algorithm employing the non‐integral value of the sampling rate delays. The FD delay filter is made adaptive and self‐learning by using least mean square algorithm. The designed synchronization technique meets the objective of faithfully tracking the phase of the grid voltage under all grid disturbances such as under voltage, overvoltage, frequency variations, and phase angle disturbances in a precise manner. [ABSTRACT FROM AUTHOR]

One cycle control (OCC) is widely used for grid current control owing to least number of sensors used, reduced complexities and cost. A proportional multi-resonant controller within the OCC is implemented in this paper for the purpose of further improvement in grid current THD. A trapezoidal PWM is proposed to reduce the DC voltage requirement for a grid-connected inverter as well as to reduce the switching losses of the inverter and hence improve the efficiency. No extra sensors are used for the implementation of trapezoidal modulation. Overall, the proposed modulation and control strategy for the inverters not only further reduces the DC voltage requirement, the number of sensors and the total switching loss, but also improves the grid current THD. Three cases are compared and verified experimentally. In Case I, a traditional PMR controller is used for the purpose of current control. In Case II, a trapezoidal PWM along with PMR control technique is proposed, whereas in Case III, trapezoidal modulation along with PMR-OCC is proposed. Experimental results and analysis show the superior performance of trapezoidal PWM along with the proposed PMR-OCC compared to that with the other two techniques. [ABSTRACT FROM AUTHOR]

This article dealt the application of three-phase all-pass filter integrated with phase-locked loop (3Ø-APF-PLL) control approach in islanded electrical supply system for enhanced power quality (PQ). It also covers the effectiveness of proposed control under various operating conditions such as intermittent wind speed, variable solar irradiance, and unbalanced nonlinear load. An islanded electrical supply system includes wind energy generation, solar photovoltaic (SPV), and battery energy storage (BES). The proposed control technique provides a coordinated and balanced operation under a dynamical load. A 3Ø-APL-PLL-based control approach is proposed to extract the maximum value of fundamental component of load current and phase angle. The proposed control approach is utilized to operate voltage source converter (VSC) that performs multi-functions, such as reducing source current harmonics, power compensation (real & reactive), balancing of loads, and improving the overall power quality of the islanded SPV-wind-BES electrical supply system. The SPV system is developed using an incremental conductance (IC)-based maximum power point tracking (MPPT) technique to extract maximum power during the intermittent conditions of solar irradiance. A bidirectional controller (BDC) is designed to operate the charging/discharging modes of a BES. Generally, an islanded electrical supply system suffers from poor voltage & frequency regulation due to the intermittency of power generation sources, which can be solved by utilizing a BES with BDC control to manage the power leveling between the power generation sources and the unbalanced load. A 3Ø-APF-PLL control approach is compared to existing controllers like a least mean square (LMS) (Singh et al. in IET Power Electron 13:2767–2774, 2020) and second-order generalized integrator-based frequency locked loop (SOGI-FLL) (Golestan et al. in IEEE Trans Power Electron 34:213–224, 2018). Numerous parameters, such as the evaluation of the maximum value of the fundamental component, stability, steady-state error, and harmonic compensation capabilities, are taken into account when comparing 3Ø-APF-PLL to the control approaches described above. The dynamic parameters of the islanded electrical supply system are justified under the IEEE-519 standard. [ABSTRACT FROM AUTHOR]

We demonstrate coherent optical frequency dissemination over a distance of 972 km by cascading two spans where the phase noise is passively compensated for. Instead of employing a phase discriminator and a phase locking loop in the conventional active phase control scheme, the passive phase noise cancellation is realized by feeding double-trip beat-note frequency to the driver of the acoustic optical modulator at the local site. This passive scheme exhibits fine robustness and reliability, making it suitable for long-distance and noisy fiber links. An optical regeneration station is used in the link for signal amplification and cascaded transmission. The phase noise cancellation and transfer instability of the 972-km link is investigated, and transfer instability of 1.1 × 10−19 at 104 s is achieved. This work provides a promising method for realizing optical frequency distribution over thousands of kilometers by using fiber links. [ABSTRACT FROM AUTHOR]

A differential ring CMOS voltage-controlled oscillator (VCO) with dual-delay path topology is proposed in this paper. In this work, the focus area is to improve the tuning range of VCO and phase noise performance of the VCO. The dual-delay path topology is used with P-MOS as load in series with negative-skewed delay transistors. This design gives the wider tuning range and this increases the phase noise performance of the VCO. After the post-layout simulation, frequency tuning range and power dissipation range are 730 MHz to 2.81 GHz and from 1.32 mW to 4.62 mW respectively. The phase noise for this VCO is −97.35 dBc/Hz at 1 MHz offset. The technology used in this work was taken from the library of SCL 180 nm technology. This design exhibits excellent phase noise performance. [ABSTRACT FROM AUTHOR]

In recent years, several research works have addressed and developed the phase-locked loop (PLL) in single-phase grid-connected converters with different structures and properties. Each has merits and demerits, such as a complex structure, high computational burden, and slow transient response. This paper aims to comprehensively review advanced single-phase PLLs based on transport delay operators to realize signal orthogonality. A deep insight into the PLLs' small-signal modeling, main characteristics, stability analysis, and loop filter design are provided in this paper. The main advantages and drawbacks are explained for each type of PLL in terms of different performance indexes, such as settling time, estimation error, and ripples in the estimated grid information. This paper also aims to provide optimal tuning and design of the loop filter gains from the large-signal model point of view, including all the nonlinearities, adopting the stochastic optimization method. All simulations are implemented using the MATLAB/Simulink 2018b environment to validate all theoretical analyses of this paper. The sampling and nominal frequencies are set to be 100 kHz and 50 Hz throughout all the simulation studies. [ABSTRACT FROM AUTHOR]

The phase‐locked loop (PLL) is a critical control module applied in the control system of renewable energy sources (RESs) to synchronize with the grid voltage. When a fault occurs, the dynamic response process of the PLL will generate a phase locking error, resulting in a mass of harmonic components in the fault current of the PV inverter, which further poses challenges to transformer differential protection. To address the challenges posed by the phase locking error in practical engineering applications, this paper proposes an improved scheme that uses a digital computer algorithm to record and store the pre‐fault voltage and introduces the limiting coefficient. Firstly, the memory voltage is used to eliminate the phase locking error of the PLL, thereby mitigating harmonic distortion in the fault current of the RESs and ensuring the reliability of the transformer differential protection. In addition, the limiting coefficient is introduced to eliminate the effect of the increased amplitude of the fault current caused by the memory voltage. The voltage reference value of the inverter is multiplied by an appropriate limiting coefficient k and then output to the physical system. Finally, the effectiveness of the proposed scheme is verified by MATLAB/Simulink simulation. [ABSTRACT FROM AUTHOR]

To address the problem of unreliable single-link underwater acoustic communication caused by large signal delays and strong multipath effects in shallow water environments, this paper proposes a distributed underwater acoustic diversity communication system (DUA-DCS). DUA-DCS employs a maneuverable distributed cross-medium buoy network to form multiple distributed, non-coherent, and parallel communication links. In the uplink, a receiving diversity processing mechanism of joint decision feedback equalizer embedded phase-locked loop and maximum signal-to-interference ratio combining (DFE-PLL-MSIRC) is proposed to achieve waveform-level diversity combining of underwater signals. A phase-locked loop module is embedded in each branch of the decision feedback equalizer to eliminate the residual frequency and phase errors after Doppler compensation. Meanwhile, the combining coefficients are determined based on the maximum signal-to-interference ratio criterion, taking into account the residual inter-symbol interference after equalization, resulting in efficient and accurate computation. Additionally, the combined decision values are fed back to the feedback filters in each branch to ensure more accurate feedback output. Simulation and lake experiment results demonstrate that, compared to the single-link communication system, DFE-PLL-MSIRC can achieve a diversity gain of more than 5.2 dB and obtain about 3 dB more diversity gain than the comparison algorithm. And the BER of DFE-PLL-MSIRC can be reduced by at least one order of magnitude, which is lower by at least 0.6 order of magnitude compared to the comparison algorithm. In the downlink, a transmitting diversity processing mechanism of complex orthogonal space-time block coding (COSTBC) is proposed. By utilizing a newly designed generalized complex orthogonal transmission matrix, complete transmission diversity can be achieved at the coding rate of 3/4. Compared to the single-link communication system, the system can achieve a diversity gain of more than 6 dB. [ABSTRACT FROM AUTHOR]

The high‐frequency circuits used in communication systems significantly depend on the functioning of the Phase‐Locked Loop (PLL). The power consumption is traded with the performance in the high‐frequency PLL. The proposed robust Phase and Frequency Detector (PFD) has multiple benefits of low‐power and reliable functioning at high frequency. The PFD highly contributes to the stable performance of the PLL, and this work proposes a 10T PFD for low‐power. The proposed PFD employs Gate Diffusion Input (GDI) logic based D‐flip flop and the pass transistor logic in the reset path to reduce power consumption. The PFD uses only 10 transistors, enabling a faster reset path and consuming less power at high frequencies. The 10T PFD was designed using 90 nm CMOS PDKs and simulated using CADENCE Specter for functional verification and performance analysis. The 10T PFD achieved a reset time of 61.4 ps at 3 GHz alongside a power consumption of 189.2 nW. Also, the overall power consumption of PLL using the proposed PFD at 3 GHz was 103.2μW demonstrating the effectiveness of 10T PFD over other conventional PFDs. [ABSTRACT FROM AUTHOR]

Although the Lissajous frequency modulated (LFM) mode can improve the long-term and temperature stability of the scale factor (SF) for mode mismatch MEMS gyroscopes, its SF nonlinearity poses a significant limitation for full-scale accuracy maintenance. This paper examines the interaction effects among stiffness coupling, system phase delay, readout demodulation phase shift, and velocity amplitude mismatch within the control process. Based on the completion of frequency difference control and demodulation phase matching, we clarify that the remaining stiffness coupling and residual system phase error are the primary factors influencing SF nonlinearity. Furthermore, SF nonlinearity is reduced through error compensation. On one hand, this paper suppresses stiffness coupling through the observation of the instantaneous frequency difference and the application of the quadrature voltage. On the other hand, system phase error is compensated by observing the amplitude control force and tuning the reference in the Phase-Locked Loops (PLLs). Subsequent simulations of these methods demonstrated a remarkable 97% reduction in SF nonlinearity within the measurement range of ±500°/s. In addition, an observed rule dictates that maintaining a sufficiently large frequency split effectively constrains the SF nonlinearity. [ABSTRACT FROM AUTHOR]

The central components influencing future grid stability in the future are inverters and their controllers. This paper delves into the pivotal role of inverters and their controllers in shaping the future stability of grids. Focusing on grid-supporting inverters, the study utilizes a microgrid test setup to explore their impact on overall grid stability. Employing impedance-based stability analysis with the Nyquist criterion, the paper introduces variations in internal inverter parameters and external grid parameters using pole-zero map considerations. The inverter's control structure, resembling standard generators with droop control, facilitates the application of grid operators' knowledge to inverter control. Mathematical insights into stability principles are provided, highlighting the influence of poles related to the phase-locked loop and the strategic placement of additional poles for enhanced stability. Furthermore, the paper evaluates the effects of rotating inertia, revealing that a 50% increase in system inertia can stabilize unstable microgrid behavior, enabling grid-supporting inverters to actively contribute to grid reliability. [ABSTRACT FROM AUTHOR]

In this work, the phase lock loop PLL-based controller has been adopted for tracking the resonant frequency to achieve maximum power transfer between the power source and the resonant load. The soft switching approach has been obtained to reduce switching losses and improve the overall efficiency of the induction heating system. The jury’s stability test has been used to evaluate the system’s stability. In this article, a multilevel inverter has been used with a series resonant load for an induction heating system to clarify the effectiveness of using it over the conventional full-bridge inverter used for induction heating purposes. Reduced switches five-level inverter has been implemented to minimize switching losses, the number of drive circuits, and the control circuit’s complexity. A comparison has been made between the conventional induction heating system with full bridge inverter and the induction heating system with five level inverter in terms of overall efficiency and total harmonic distortion THD. MATLAB/ SIMULINK has been used for modeling and analysis. The mathematical analysis associated with simulation results shows that the proposed topology and control system performs well. [ABSTRACT FROM AUTHOR]

In control and communications, the phase-locked loop (PLL) is regarded as the demodulator. Under the presence of small noise, the PLL system fails to accomplish the locking condition resulting in the stochastic phase difference. As a result of this, the PLL becomes a nontrivial nonlinear stochastic system. To circumvent the curse of dimensionality and nonlinearity, we exploit the method of linearization in the Carleman framework in combination with the finite closure for the stochastic system considered here. We show that the Carleman linearization has proven useful to preserve the nonlinearity via bilinearization. The Carleman setup of the nonlinear stochastic differential system has the Markov property and the terms are manageable. Then, we filter the states of the PLL using the filtering theory of the homogeneous Markov process. Finally, the numerical simulations reveal the superiority of the proposed filtering in Carleman setting in contrasts with the celebrated extended Kalman filtering framework. [ABSTRACT FROM AUTHOR]

In this work, an optimal phase locked loop (PLL) is employed to estimate the fundamental grid frequency and phase angle under grid disturbances, which largely reduces the frequency and phase error. Conventional synchronous reference frame (SRF) offers considerable results for balanced grid conditions but has poor performance under grid disturbances with improper phase detection. In this regard, gravitational search algorithm (GSA)‐based optimization is utilized to optimally tune the proportional and integral (PI) gain values of conventional SRF PLL, which ensures the proper tracking of fundamental phase angle and frequency even during abnormal grid conditions, that is, voltage unbalance, frequency variations, high‐frequency harmonics, and phase variations. Further, integral square error (ISE) criteria, settling time, and overshoot are considered as objective functions to obtain the optimal value of current gain, present in the control loop of a grid‐tied solar photovoltaic (PV) system. The supremacy of the proposed work, compared to SRF and optimal SRF PLL, is tested with MATLAB®/Simulink studies and verified by dSPACE‐1104‐based hardware‐in‐loop (HIL) results for real‐time validation. [ABSTRACT FROM AUTHOR]

Summary: The time delay unit‐based PLLs (TD‐PLLs) are widely used in grid synchronization in single‐phase power systems. However, the TD‐PLL is vulnerable to frequency variations and harmonic disturbances, leading to grid synchronization failures. Analysis shows that the performance degradation is due to the inability to obtain the variation of the input signal frequency. This paper proposes a new time delay‐based phase‐locked loop called immune to double frequency component TD‐PLL (IDFC‐TD‐PLL) based on a feedback structure to accurately capture the variation of input signal frequency, which can improve the dynamic performance and the performance against harmonic interference. Simulations and experiments have evaluated the performance of the proposed phase‐locked loop, demonstrating its superior accuracy and dynamic performance compared to the phase‐locked loops referred in the paper. [ABSTRACT FROM AUTHOR]

This paper presents a modification of class D zero-voltage-switching (D-ZVS) resonant inverter for ultrasonic cleaning applications. The output power is controlled using the adjustable duty of a buck converter. Combined with a phase-locked loop control, the switching frequency of the inverter is automatically adjusted to maintain a lagging phase angle under load–parameter variations during the cleaning process. With the proposed modification, the inverter maintains ZVS throughout the power control range. Moreover, the snubber capacitor connection is used to reduce turn-off losses. The control algorithms are implemented using digital signal processing (TMS320F28335 for buck converter and TMS320F28379D for inverter). The proposed method for a 100-W piezoceramic ultrasonic transducer (PZT) is verified using computer simulation and laboratory experimental results and is found to be more efficient than other methods. The operating frequency and power ranges under investigation are 36.5–36.96 kHz and 15–95 W, respectively. [ABSTRACT FROM AUTHOR]

The mode localization phenomenon of the weakly coupled resonators (WCRs), which is revealed as a small asymmetric perturbation introduced in the symmetric weakly coupled resonant system will lead to a drastic variation in the system energy distribution and amplitude ratios of the resonators, has been widely used in the topology design of micro-electro-mechanical system (MEMS) sensors. In order to improve the noise characteristics of mode-localized sensors, this paper presents an optimized measurement and control system, including the frequency closed-loop system based on phase-locked loop (PLL) and the amplitude closed-loop system based on energy conservation. The vibration energy of a weakly coupled resonant system can be represented by the sum of the squares of the amplitude of each resonant unit, and the total energy of resonant units is stabilized at a constant value by the amplitude closed-loop system based on energy conservation. The proposed measurement and control system is optimized by Simulink simulation software and finally verified with the fabricated prototype of a mode-localized airflow sensor. Experiment results demonstrate that compared with the amplitude open-loop detection method, the closed-loop control scheme based on energy conservation has better bias stability, which indicates that our proposal can improve the long-term stability of output signals of the weakly coupled resonant system. [ABSTRACT FROM AUTHOR]

In this paper, we propose an mm-wave local oscillator generation (LOG) method based on a voltage-controlled oscillator (VCO) with low phase noise (PN) and a novel injection-locked frequency tripler (ILFT), which can significantly improve the PN performance and power efficiency. The VCO features the source-to-gate feedback architecture with a third-impedance enhancement transformer so that the fundamental signal with the boosted third-harmonic output voltage in the source terminal is delivered to ILFT and the relatively pure 20-GHz signal from the gate node can be fed back to the phase-locked loop (PLL). The proposed ILFT adopts the high-order transformer-based resonator, injection-current-boosting (ICB), and class-D tail-switching techniques leading to a wide locking range (LR). Designed and simulated in 40-nm CMOS technology, the post-simulation results exhibit 1-MHz offset PN of better than −102 dBc/Hz over a continuous frequency tuning range (FTR) of 10.9% from 56.6 to 63.1 GHz while consuming 23.5 mW. The figure-of-merit (FoM) achieves up to 186.2 dBc/Hz at 1-MHz offset. [ABSTRACT FROM AUTHOR]

A novel delay cell circuit for differential ring oscillator (DRO) with large tuning range along with application in charge pump phase lock loop (CP-PLL) frequency synthesizer has been presented in this paper. Using 0.18 μ m CMOS technology with power supply of 1.8 V, the two DRO architectures: 3-stage and 5-stage, were built and simulated. In both 3-stage and 5-stage DROs, single controlled voltage is employed. The suggested 3-stage and 5-stage DRO circuits generate a tuning range of 96.77 MHz - 5.296 GHz and 36.33 MHz - 2.803 GHz, respectively. The % total harmonic distortion (%THD) of both DRO architectures is also evaluated. The suggested 3-stage and 5-stage DROs consume 6.63 mW and 11.05 mW power at an oscillation frequency of 4.76 GHz and 2.479 GHz, respectively. At an offset frequency of 10 MHz from the oscillation frequency, the proposed circuits have phase noise of - 119.93 dBc/Hz and - 128.24 dBc/Hz, respectively. The layout of proposed design has been drawn and pre- and post-layout simulation results show satisfactory variations of tuning range and phase noise of proposed design. The suggested circuit's robustness is verified with the help of PVT and Monte Carlo analysis. When compared to contemporary research, the proposed DROs have the widest tuning range. Proposed DRO application in CP-PLL frequency synthesizer has locking time of 1.17 μ s and shows good settling behaviour with dynamic parameter variations. [ABSTRACT FROM AUTHOR]

As the boost of power electronics technology, the harmonic problem in the power system is becoming increasingly prominent. Fourier decomposition is performed on the load current in the power system, and components with a frequency that is an integer multiple of the fundamental wave are referred to as harmonic components. Harmonic control is essential to establish a safe and reliable power grid environment and provide high-quality and clean electricity to power users. The study focused on parallel active power filters, proposed a specific harmonic detection method on the grounds of synchronous harmonic rotating coordinate system, and developed a phase-locked loop design on the grounds of order generalized integrator. Meanwhile, a compensation current control method on the grounds of space vector pulse width modulation was introduced. The results showed that in the full compensation simulation experiment, the compensated A-phase grid side current waveform was significantly improved and presented a sinusoidal shape. After 0.05 s, the actual output compensation current closely followed the command current. Meanwhile, after compensation, the total harmonic distortion rate decreased from 26.58 to 3.06%. In specific harmonic compensation simulation experiments, when the sum of 5th, 7th, and 11th harmonic components was used as the command current for compensation, the distortion of the current waveform was improved after the load undergoes a sudden change. After compensation, the 5th, 7th, and 11th harmonic content significantly decreased, and the total harmonic distortion rate decreased to 4.08%. This indicated that the proposed phase-locked loop design and harmonic detection method for active power filters had high stability and effectiveness. The study's primary contribution is to enhance the utilization efficiency of DC voltage and improve the dynamic response ability of current. Additionally, it offers a new method for reducing the impact of harmonics on the power grid and improving power quality. It provided an effective method reference for technological progress in related fields such as power electronics and control engineering. [ABSTRACT FROM AUTHOR]

This paper presents a new process, voltage and temperature (PVT) tolerant 7-stage ring type current starved voltage-controlled oscillator (CS-VCO). In this, a 7-stage ring VCO is proposed using power gated technique for phase locked loop (PLL) application. PLL plays a major role in clock and data recovery, Global Positioning System (GPS) system and satellite communications. For the high-speed application of PLL it is designed using 7-stage inverter delay cell with MOS current mode logic (MCML) technique. The circuit undergoes process, voltage and temperature variations with different parameters such as average power, oscillation frequency, phase noise, tuning range and output noise. The Monte-Carlo analysis justifies the proposed design provides better results. The circuit is simulated under 45 nm CMOS technology using cadence virtuoso. The average power consumption of the proposed circuit is 29.368 µW with the oscillation frequency of 3.06 GHz. The output noise and the phase noise of the proposed VCO are -161.55 dB and -125.92 dBc/Hz respectively. It achieves the frequency tuning range (FTR) of 95.09 %. The obtained simulation results are highly robust with PVT making the circuit suitable for PLL application. [ABSTRACT FROM AUTHOR]

The purpose of this paper is to propose a novel technique for extracting the position signal from an inductive displacement transducer named a linear variable differential transformer (LVDT). In general, the movement of the LVDT core causes its primary inductance change in linear form. The primary winding of the LVDT is used as a time-dependent element for the triangular and square wave generator, which can be called self-oscillation, to generate frequency. The advantage of the proposed technique is that it can measure the displacement using the LVDT without an external oscillator. The change in primary inductance causes the frequency deviation generated by the oscillator. The deviated frequency is captured and converted into a voltage signal using the principle of the phase-locked loop. All the components used in this study are commercially available. The merits of this proposed technique are simple configuration, small size, and low cost. Moreover, the operating range of the LVDT can be extended without the limitation of the nonlinear transfer characteristic. The performance of the proposed technique is discussed in detail and confirmed by experimental implementation. Experimental results show that the maximum error from the proposed technique is about 0.42% and the operating range of the LVDT can be extended to more than 200%. It can be seen that the proposed technique is suitable for embedded measurement in small or micro robots. [ABSTRACT FROM AUTHOR]

This paper delves into a comprehensive study of a wide-speed-range sensorless control approach for surface-mounted permanent magnet synchronous motors (SPMSMs). In the low-speed range, a novel high-frequency pulse voltage injection (HFPVI) method is introduced for rotor position estimation, which does not depend on motor saliency and is well-suited for SPMSMs. This method incorporates a second-order generalized integrator (SOGI) and a new modulation signal to enhance the accuracy of rotor position estimation. For medium-to-high speeds, an improved super-twisting sliding mode observer (STSMO) utilizing a continuous hyperbolic tangent function is proposed to mitigate chattering. Additionally, a new phase-locked loop (NPLL) is introduced to accurately obtain the rotor position. Furthermore, this paper designs an exponential weighted switching function to facilitate a smooth transition of the motor from the low-speed domain to the medium- and high-speed domains. The effectiveness and superiority of the proposed methods are validated through simulations and experiments conducted on an RTU-BOX platform. The rotor position estimation errors of the proposed new HFPVI method and the improved STSMO method under various operating conditions are both approximately 0.05 rad (2.8 elc·deg), and the SPMSM can switch smoothly from the low-speed range to the medium- and high-speed ranges. [ABSTRACT FROM AUTHOR]

This article presents the development and implementation of an integer N-type Phase Locked Loop (PLL) module with two output frequencies of 1 and 4 GHz, each having a loop phase noise better than -110 dBc/Hz@10k. The structure has power levels of 0 and 10dBm at 1 and 4 GHz output frequencies, respectively. Having two different outputs of 1 and 4 GHz at once, in addition to the 1.1 and 4.4 GHz output frequencies realized by the capability included in this design in which two additional outputs can be achieved by using the pins A0 to A4 and altering their status, makes this structure a good candidate for mass production. A two-step frequency division is employed in this work. The first step is realized using the frequency divider of order 4, and the second step is implemented inside the HMC440 IC, including a PFD and a counter so that the output frequency approaches the closest to the reference frequency. Compared to the typical methods, this method presents a clean output by suppressing the spurs meant to be manifested using a single-step frequency division. This PLL is constructed in discrete and modular modes and employed in transceivers' up-converter and down-converter blocks, Satellite communications, Cable TV links (CATV), Local Area Networks (LAN), Global Positioning Systems (GPS), test equipment, digital radios, military and commercial communications. For a specific example, the 4-GHz frequency is used to up-converte or down-converte the received signals, and the 1-GHz frequency is usually used for the synthesizer module clock frequency. Advanced Design System (ADS) software was used in the design of the low-pass filter part of the loop, and OrCAD software was used in the schematic design of the phase lock loop module. [ABSTRACT FROM AUTHOR]

To generate high frequency signals for frequency modulated continuous wave (FMCW) application, components such as doubler, tripler or multiplier are usually utilized to process further signals from the low frequency voltage controlled oscillator (VCO). In this paper, a phase-locked loop (PLL) is intended to be the primary part used to generate frequency modulated continuous wave (FMCW) signals from 80 to 84.8 GHz by utilizing a fundamental frequency VCO. To divide those high frequency output signal and large output bandwidth, the auto-tracking Miller divider topology is proposed. This new topology can achieve 9 GHz locking range. In order to generate FMCW signals with a straight-line triangular chirp, the cascaded PLL is used. The integrated jitter from 1 kHz to 1 GHz is 887 fs for the cascaded PLL, while the single stage PLL used 1.264 ps. Moreover, when architecture with doubler or multiplier is used, the fundamental tone has an effect towards the next systems, while the cascaded PLL does not. It can be highlighted that this work achieves the best RMS-FMerror/BWchirp and RMS-FMerror/(BWchirp × fc × Tc) with value of 0.013% and 0.77e−12, respectively. The designed PLL for FMCW signal generator is implemented in 28 nm CMOS technology. By using a supply voltage of 1.2 V, the chip consumes power of 102 mW. Including all the chip pads, the implemented circuit occupies a silicon area of 1440 µm × 820 µm. [ABSTRACT FROM AUTHOR]

This paper presents a wideband approach for L5 and S-band integer-N phase-locked loop (PLL) targeting Indian Regional Navigation Satellite System (IRNSS) applications. A reference spur reduction technique using a G m − C filter is proposed. The reference spur is improved by 7 dB when compared with one without any G m − C filter. The wideband integer-N PLL is designed and fabricated in UMC 65-nm CMOS process. The G m − C filter block consumes 200 μ A current. The wideband voltage-controlled oscillator (VCO) oscillates from 1.6 GHz to 3.2 GHz having a tuning range (TR) of 40 % , achieving a best and worst phase noise of ≈−122 dBc/Hz and ≈ − 116 dBc/Hz at a 1 MHz offset, respectively. [ABSTRACT FROM AUTHOR]

In order to improve the stability of sensorless high-speed operation of permanent magnet synchronous motors and effectively expand the speed range, a voltage closed-loop flux weakening sensorless algorithm based on the active flux model is proposed. Firstly, the mathematical model of sensorless control of the PMSM is designed based on the active flux model, and the state of the PMSM flux weakening operation is analyzed. Then, based on the voltage closed-loop flux weakening control method, the corresponding flux weakening control algorithm is analyzed and designed. Meanwhile, based on the active flux model, the speed and rotor position of the motor are observed by sliding mode observer and phase-locked loop method. After that, the flux weakening control method and sensorless control method are combined to realize the sensorless flux weakening control method to improve the stability of the control system. Finally, the proposed algorithm is validated on the experimental platform. The experimental results show that the proposed method can prevent the system from losing control during flux weakening processes, effectively improve system stability, and have smaller angle errors. The speed convergence time is shortened by 80% compared to the non flux weakening control. [ABSTRACT FROM AUTHOR]

The purpose of this paper is to study the sensor-less rotor position estimation method for permanent magnet synchronous motors, and to achieve accurate estimation of rotor position in different conditions. Firstly, the traditional super-twisting observer algorithm is analyzed, and a new discrete variable gain sliding mode observer is designed to solve the buffeting problem in discrete systems, taking the reaction force as the disturbance signal. By estimating the back potential of the observer, the buffeting problem in the sliding mode algorithm can be effectively improved as shown by the simulation results. Then, to solve the problem of phase delay in rotor position estimation, an adaptive orthogonal phase-locked loop method is used to compensate the estimation error caused by the change in motor speed and increase the estimation accuracy of rotor position. The stability of the method can be proven by Lyapunov's second method. Simulation experiments verify the accuracy of the proposed PMSM rotor position estimation method. [ABSTRACT FROM AUTHOR]

To ensure precise phase estimation within the q-axis of the phase-locked loop (PLL), integrating a filter into the q-axis loop is essential to mitigate grid-voltage harmonics. Nevertheless, the intrinsic delay characteristics of this filter impede PLL synchronization during significant grid disturbances. This study begins by developing mathematical models for three types of filters—moving-average filter (MAF) for eliminating odd harmonic components, dq-frame cascaded delayed signal cancellation (dqCDSC) filter, and notch filter (NF). Following the reduction in filter orders, a third-order nonlinear large-signal model of the PLL, incorporating an additional q-axis internal filter, is formulated. Using phase plane analysis, this study investigates the transient synchronism of the grid-following converter (GFL) and explores the influence of delay time constants from the three PLL filters on its behavior while delineating the boundaries of their basins of attraction. Theoretical findings indicate that, relative to the traditional SRF-PLL, incorporating an internal filter into the PLL compromises the transient synchronous stability of GFL. Specifically, greater filter delay time constants exacerbate the GFL's vulnerability to transient instability amid substantial grid disturbances. Hence, careful consideration is essential when using MAF-PLL and NF-PLL in situations demanding high synchronization stability. The theoretical analyses are validated using Matlab/Simulink to verify their accuracy. [ABSTRACT FROM AUTHOR]

Abstract In the case of grid voltage quality problems, the traditional phase‐locked loop (PLL) is hard to detect the accurate grid frequency and phase during the transient response, which will be detrimental to the transient synchronous stability of grid‐connected inverters. This paper proposes a mode switching based transient ride‐through PLL (TRT‐PLL), aiming to improve the transient phase‐locking performance through detection technique and mode switching. The TRT‐PLL incorporates a hybrid filter (HF), a dual‐speed detection module, and a state switch into the traditional synchronous reference frame PLL (SRF‐PLL) structure. The theoretical analysis and paradigm design of TRT‐PLL is presented in detail. Digital simulations and physical experiments are carried out for the comparisons with other existed PLL techniques. The results demonstrate that the satisfied transient performance of the TRT‐PLL has significant advantages, especially in the event of phase jumps.

This work reports load-frequency-control (LFC) of a three-area hybrid power system incorporating renewables and electric-vehicles (EV). Such a power system with applicable non-linearities necessitates a resilient controller. In this respect, a multi-stage fractional-order proportional-integral-derivative (MSFOPID) controller is explored for the LFC operation of the presented hybrid power system. For the proposed controller, there is a considerable improvement of 81.3% in terms of objective function (ISE value). Similarly, the foible evidence study shows an improvement of 39% with respect to other considered secondary controllers. The active role of EVs in preserving the system dynamics is inspected thoroughly. The impact of redox-flow batteries as an energy storage device and parametric variation of phase-locked-loop for system dynamic control are illustrated. Furthermore, the robustness of explored MSFOPID controller optimized gains is checked against alterations in power-system-loading and renewable energy sources, respectively. [ABSTRACT FROM AUTHOR]

This paper proposes a phase-locked loop (PLL) with a low bandwidth and high estimation performance in terms of position and speed through speed feedforward compensation for driving extended back electromotive force (EEMF)-based sensorless control for an interior permanent magnet synchronous motor (IPMSM). In this case, lowering the bandwidth to reduce sensitivity to disturbances of the PI controller, where the position error is controlled to zero, may create a problem of decreased estimation performance. The proposed method calculates speed through mathematical calculations of the EEMF, which is observed using an EEMF-based IPMSM model, and adds it to the output of the PLL. The added speed feedforward compensation reduces the computational burden of the PI controller. Therefore, fast estimation dynamic characteristics can be obtained even at low bandwidths. The improvement of the estimation performance of the proposed method is evaluated by analyzing the equivalent block diagram using the final value theorem theory. Through this, the estimation performance is shown. It can be seen that the position estimation error for various types of speed inputs converges to zero. In addition, validity and implementation of this method are verified by experimental results. [ABSTRACT FROM AUTHOR]

The phase frequency detector (PFD) is an important component in a phase-locked loop (PLL). PFD detects the timing difference between the reference clock (REFCK) and the feedback clock (FBCK). PFD plays a major role in deciding the amount of time required by a PLL to achieve lock. The blind zone in the PFD causes inaccurate PFD output. This negatively impacts the PLL's lock-in time. The increase in lock-in time poses great challenges for developing high-speed PLLs. This paper proposes a PFD architecture that eliminates the reset pulse when the timing difference between the REFCK and the FBCK is significantly high. The elimination of the reset pulse in this way leads to a blind zone free PFD across process, voltage, and temperature (PVT) variations. The PFD is realized and implemented in the Cadence spectre environment using the UMC 0.18 μ m CMOS process. From the results, it can be stated that the designed PFD is blind zone free across PVT variations. The proposed PFD-based PLL locks faster than the traditional PFD-based PLL. The proposed PFD consumes 163 μ W power at a 100 MHz operating frequency which is the lowest compared to the earlier reported works. Its operational range is [ - 2 π , 2 π ]. The PFD occupies an area of 0.0069 mm 2 . The proposed design is well suited to low-power, high-speed PLL applications. [ABSTRACT FROM AUTHOR]

This paper presents the development of advanced adaptive controller for dynamic voltage restorer (DVR) to regulate the power quality connected to a distribution system. Various voltage quality issues have been generated as distorted grid conditions are responsible for abnormal operation of the consumer electronics and domestic household appliances. Therefore dynamic voltage restorer (DVR) is employed for elimination of voltage quality issues in the distribution lines. To improve the performance and efficiency of DVR, an improved robust SRF (IR-SRF) controller has been developed in this paper for the mitigation of voltage quality issues under weak grid conditions. In the developed IR-SRF controller, moving average filter (MAF) has been utilized for better extraction of ripples from the sensed voltage. For better grid voltage signal synchronization with the proposed controller under highly dynamic condition, an enhanced Phase Locked Loop (PLL) scheme has been utilized instead of conventional PLL. For the regulation of DC link voltage under dynamic environmental conditions, MAF based fuzzy tuned PI controller has been utilized with the ability to adapt the situation. The developed controller has been simulated and results for various grid voltage conditions have been analyzed. The obtained simulation results are compared with conventional control algorithm to validate the efficacy. The efficiency of the proposed controller has been validated using the experimental results. [ABSTRACT FROM AUTHOR]

This paper proposes an improved version of Synchronous Reference Frame (SRF) based phase locked loop (PLL). The conventional SRF-PLL structure is modified and made adaptive using a Least Means Square (LMS) algorithm. The benefit of the proposed scheme is that the tuning of proportional controller (PI) gain parameters can be achieved automatically without having to optimise these parameters manually. The PLL is utilised to track important electrical grid parameters such as phase angle, unit synchronisation templates and voltage magnitude. This performance study investigates several cases such as voltage sag/swell, wide frequency deviation, phase jump, presence of noise and harmonics in the supply voltage. The impact of constant and adaptive PI parameters influencing PLL performance is investigated. Finally, a fair comparison is presented which discusses the proposed adaptive SRF-PLL(ASRF-PLL), conventional fixed gain SRF-PLL, unit template-based synchronisation technique and Delayed Signal Cancellation based PLL (DSC-PLL). [ABSTRACT FROM AUTHOR]